The increasing reliance upon computer systems to collect, process, and analyze data has led to the continuous improvement of the system assembly process and associated hardware. With the improvements in speed and density of integrated circuits, the cost and complexities of designing and testing these integrated circuits has dramatically increased. Currently, integrated multi-functional Electronic Automation Design (EAD) tools are used to design and simulate integrated circuit devices. The design of an integrated circuit involves synthesizing device components to meet the device specification, including requirements for both device functionality and device timing. The design is typically verified against the device specification via simulation. A simulator, typically integrated into the EAD tool, simulates the operation of the design by applying a set of input stimulus to the synthesized design, and receiving and monitoring a set of simulated output responses. The input stimulus is designed to test the functionality and timing requirements of the device specification. The simulator compares the simulated output response to expected output response values to verify operation of the design. Once a design is satisfactorily verified against the device specification, a physical implementation of the device (i.e., a “prototype”) is generated and tested using the simulation test data, including respective pairs of input stimulus and expected output response to verify expected operation of the physical device against the design.
Simulator tools generally output simulation test data, including respective pairs of input stimulus and expected output response, to files implementing what is known in the industry as “event-based” data formats. Examples of such event-based data formats include the IEEE Standard 1364-2001 Virology Change Dump (VCD) format, or the IEEE Standard 1450-1999 Standard Test Interface Language (STIL) format. A VCD event-based data file, for example, typically contains header information, variable definitions (e.g., pin number or name definitions), and the timescale used. Next, the file typically contains definitions of the scope and type of variables being dumped, followed by the actual value changes at each simulation time increment. Only the variables that change value during a time increment are listed.
In contrast, the integrated circuit testers, typically large complex industrial Automated Test Equipment (ATE), operate according to fixed device cycles. Accordingly, ATE typically requires input test data in files implemented according to a “cycle-based” data format. A cycle-based data format generally includes a set of vectors and a set of waveforms defined by a fixed device cycle time.
The event-based data file format and cycle-based data file format are incompatible. Accordingly, in order to utilize the simulation test data generated by the simulator to verify operation of the prototype, or to verify operation of manufactured devices during production, the event-based simulation test data file must be converted to a cycle-based test data file(s) compatible with the ATE.
A translator tool typically performs the conversion of event-based simulation test data files to cycle-based test data file(s) appropriate for the particular ATE testing the prototype or device under test (DUT). One incompatibility problem with event-based simulation test data is that event-based data reflects one time point for each event. In the actual silicon, however, the time that an event may occur is actually a range between the best case and worst-case extremes. Providing the device timing diagrams, which contain the ambiguity regions of the signals' timing, allows the translator tool to identify the device cycle that the simulator executes, and then to test according to the device cycle specification as it appears in the timing diagrams to generate a test according to the actual device specification. Accordingly, the translator tool essentially imposes a fixed cycle on event-based simulation test data in order to extract, from the event-based simulation test data, separate waveforms (i.e., timing diagrams characterized by a fixed set of discrete behaviors) and corresponding separate data vectors (i.e., the sequence of those discrete behaviors) implemented in the cycle-based file format required by the particular ATE that will be testing the physical device. Many integrated circuits designed and manufactured today are high-speed digital serial communication devices such as high-speed network communication devices including SerDes (Serializer/Deserializer), SONET, Gigabit Ethernet, InfiniBand and FibreChannel chips. Serial devices such as these rely on a clock signal to transmit and recover data. However, due to thermal and other variations, drift, jitter, and other timing irregularities may be introduced into the data during data transmission. To compensate for this, modern high-speed serial devices are often built to include an internal clock recovery system, and the clock signal is embedded within the serial data itself. The clock recovery circuitry on the serial receiver includes source synchronous functionality, which essentially performs a “snap to grid” on the clock signal, adjusting to any detected clock period deviations. “Source synchronous” refers to a circuit's ability to resynchronize to a clock that drifts, jitters, or exhibits other timing irregularities during data transmission.
In order to test the functionality of clock recovery circuitry on a serial device, test engineers often inject timing irregularities into the test data during simulation. This can be done manually by the design engineer, or automatically using a timing irregularity injection tool provided with the simulator. As just described, however, a conventional translator tool essentially imposes a fixed cycle on event-based simulation test data in order to extract a separate waveform (i.e., a timing diagram characterized by a fixed set of discrete behaviors) and corresponding separate data vector (the sequence of those discrete behaviors) from the simulation test data format. This is problematic when generating test vectors from a serial device simulation containing injected timing irregularities because, since the tester requires fixed period device cycles generated based on ideal device specification timing diagrams, the translator tool typically cannot match up event-based test data containing injected timing irregularities with the ideal timing diagrams of the device specification, and thus the cyclization engine is often unable to generate device cycles for this type of data. Thus, it is very difficult to generate cycle-based test data from event-based test data that contains such timing irregularities in order to test the source-synchronous hardware on these devices. Accordingly, a need exists for a tool that extracts and removes timing irregularities, such as drift and jitter, from event-based simulation test data that contains such injected timing irregularities, to generate corresponding “clean” cycle-based test data (i.e., fixed device cycles without the injected timing irregularities) in the format specific to the particular ATE testing the physical serial device. A need also exists for a technique for a tool that extracts such timing irregularities and provides the extracted timing irregularities to the ATE in a format usable by the ATE to allow the ATE to reinject the extracted timing irregularities into the “clean” cycle-based test data using the ATE's own timing irregularity injection module when testing the device.